This invention relates to synchronous circuits of the type found in many computer systems in general. More particularly, this invention relates to a synchronous circuit with improved clock to valid data output access time.
Synchronous circuits are widely used in computer systems due to the speed with which input information can be processed and made available as valid output information. Examples of such synchronous circuits are synchronous DRAMs, synchronous SRAMs and synchronous programmable logic devices. Such circuits are usually synchronized by a system clock provided by a separate system clock generator, which provides the system timing cycle for all synchronous circuits in a given system.
Current synchronous circuits typically employ one or more input registers to capture information on the input terminals, and zero or more output registers/latches in order to present the processed information emerging from the synchronous circuit to follow-on system circuitry. The registers are typically implemented as master and slave latches in which data presented to the input of the register is latched in on the rising edge of the system clock by sampling and storing input data to the master latch, and data latched in the master latch is transferred into the slave latch and latched therein on the falling edge of the system clock. When the master latch is unlatched by the system clock high to low transition, the master latch becomes transparent to any signals on the input lines thereto. Similarly, when the slave latch becomes unlatched due to a low to high transition of the system clock, the slave latch becomes transparent to any signals on the input lines thereto. The term "transparent" is understood to mean that signals appearing on the input lines pass through the latch and appear on the output lines (subject to the delay introduced by the response time of the individual circuit components making up a given latch). An example of a conventional synchronous SRAM circuit having a register consisting of a master-slave latch is shown and described in U.S. Pat. No. 5,493,530 issued Feb. 20, 1996, for "RAM with Pre-Input Register Logic", the disclosure of which is hereby incorporated by reference.
In order to guarantee the reliability of information latched into a synchronous circuit, a system designer normally specifies a parameter termed "setup time", which is a minimum time period during which the input lines must be stable (i.e., in a ready state) prior to the occurrence of a latching edge of a system clock signal. This is due to the fact that the latching edge of the system clock signal causes the various registers to sample and store the values of the connected input lines. Similarly, the system designer also normally specifies another parameter termed the "hold time" which is a minimum time period during which the input lines need to be stable immediately after the occurrence of the latching edge of the system clock signal. The time periods prior to the beginning of setup time and following the hold time are typically designated as "don't care" periods in which the state of the input lines does not affect the synchronous circuitry processing.
In the operation of a typical synchronous circuit, once the input information has been latched into the register consisting of the master-slave latch, the information output from this register is then processed by the internal or core logic circuitry to perform a desired function. For example, in a synchronous SRAM circuit, the information on the output lines from the master-slave input register is typically decoded and used to access individual memory cells for the purpose of either a read or a write operation. Taking a read operation as an example, once the individual memory cells have been properly accessed, the data contents of the cells are presented to the input lines of the output latch, output register or output buffer. At the beginning of the next system cycle, this data is latched into the output latch, output register or the input register of the follow-on circuitry, while new information is presented and latched into the input register for next system cycle processing.
In any synchronous circuit, there is a finite processing time after the presentation of the input information to the internal circuitry before valid information can be available at the output of the circuit. This processing time is termed the "delay time", and must be observed when designing synchronous circuits in order to insure that valid information will always be available for the next stage circuits or be latched into the circuit output register for presentation to the follow-on circuitry. The delay time is a function of the response time of the individual logic circuit components, as well as a function of component temperature, operating voltages, and inherent device speed.
An important parameter for synchronous circuits is the system clock to data output access time, which is the minimum time period between the latching edge of the system clock and the guaranteed appearance of correct and stable output information. In general, the smaller the system clock to data output access time, the more useful the synchronous circuit, due primarily to the increasingly high processing speeds of current computer systems. However, the system clock to data output access time in known synchronous circuits has been limited to a minimum value equal to the delay time of the internal circuits. Efforts to date to provide synchronous circuits with system clock to data access output times less than the delay time have been very limited.